The present invention relates, in general, to the field of integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (DRAM). More particularly, the present invention relates to a column read amplifier power-gating technique for DRAM devices and those devices incorporating embedded DRAM which incorporate a power-down (or Sleep) Mode of operation.
Many types of DRAM based devices, or integrated circuits including embedded memory arrays, are currently available including extended data out (“EDO”), synchronous DRAM (“SDRAM”), double data rate (“DDR”) DRAM and the like. Regardless of configuration, the primary purpose of the DRAM is to store data. Functionally, data may be written to the memory, read from it or periodically refreshed to maintain the integrity of the stored data. In current high density designs, each DRAM memory cell comprises a pass transistor coupled to an associated capacitor that may be charged to store a value representative of either a logic level “1” or “0”. Data stored in these memory cells may be read out and written to them through columns of sense amplifiers coupled to complementary bit lines interconnecting rows of these cells.
Column read amplifiers have been used in integrated memory circuits to improve the speed of reading data. For DRAMs, column read amplifiers are located adjacent to the bit line sense amplifiers and the bit lines (or sense latch nodes) are connected to the gates of a pair of transistors to control the drain-to-source current through these transistors. The sources of these transistors are generally connected to a reference voltage level of circuit ground (VSS) while their drains are connected to the sources of a pair of pass transistors. These pass transistors have their gates connected to receive a column select signal (YR) and their drains are connected to the complementary local read data lines (DR and DR bar or “DRB”).
In operation, the data lines are precharged “high” to a supply voltage level (VCC). When the column select signal YR goes “high”, one of the data lines is driven “low” depending on which bit line is “high”. Normally, the signal YR is at 0V (VSS) when the column in not selected and is at VCC when the column is selected.
Power-gating can be used to reduce Sleep Mode power. A conventional approach involves the addition of a large power-gating transistor between the column read amplifiers and VSS. Generally, there may be a large number (on the order of 1024 or more) of read amplifiers sharing a single power-gating transistor and more than one read amplifier would be activated at the same time (typically from 16 to 128 or more). The gate of the power-gating transistor is conventionally driven below VSS during Sleep Mode to reduce the current through the read amplifiers.
The difficulty with this approach is that in the Select Mode, the current surge through the power-gating transistor can be unacceptably large due to the fact that multiple read amplifiers switch simultaneously. This causes a voltage drop across the power-gating transistor which reduces the switching speed of the read amplifiers. Furthermore, as previously mentioned, the power-gating transistor must be made very large in an attempt to minimize this voltage drop, thereby also consuming a large amount of on-chip area.